1. General description

The 74AUP1G17 is a single buffer with Schmitt-trigger input. This device ensures very low static

and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is

fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output,

preventing the potentially damaging backflow current through the device when it is powered down.

2. Features and benefits

? Wide supply voltage range from 0.8 V to 3.6 V

? CMOS low power dissipation

? High noise immunity

? Overvoltage tolerant inputs to 3.6 V

? Low noise overshoot and undershoot < 10 of VCC

? IOFF circuitry provides partial Power-down mode operation

? Latch-up performance exceeds 100 mA per JESD 78 Class II Level B

? Low static power consumption; ICC = 0.9 μA (maximum)

? Complies with JEDEC standards:

? JESD8-12 (0.8 V to 1.3 V)

? JESD8-11 (0.9 V to 1.65 V)

? JESD8-7 (1.2 V to 1.95 V)

? JESD8-5 (1.8 V to 2.7 V)

? JESD8C (2.7 V to 3.6 V)

? ESD protection:

? HBM: ANSI/ESDA/JEDEC JS-001 Class 3A exceeds 5000 V

? CDM: ANSI/ESDA/JEDEC JS-002 Class C3 exceeds 1000 V

? MM: JESD22-A115-A exceeds 200 V

? Multiple package options

? Specified from -40 ° C to +85 ° C and -40 ° C to +125 ° C

74AUP1G17屬于集成電路（IC） > 觸發(fā)器。安世半導(dǎo)體(中國)有限公司制造生產(chǎn)的74AUP1G17觸發(fā)器觸發(fā)器是能夠存儲單個邏輯狀態(tài)或信息“位”的基本數(shù)字存儲器件。這些器件至少有兩個輸入；一個或多個用于傳遞要存儲的數(shù)據(jù)，另一個用于指示存儲該數(shù)據(jù)的時間點。不同的觸發(fā)器類型，例如 D（延遲）、SR（置位復(fù)位）和 JK，對提供給其輸入的信號有不同的響應(yīng)，可用于實現(xiàn)不同的邏輯功能。這些器件與鎖存器的不同之處在于它們是邊緣敏感器件，其保持的邏輯狀態(tài)僅在接收到有效時鐘信號時才會改變。