首頁>74AUP1G86>規(guī)格書詳情

74AUP1G86集成電路（IC）的門反相器規(guī)格書PDF中文資料

廠商型號	74AUP1G86
參數(shù)屬性	74AUP1G86 封裝/外殼為6-XFDFN；包裝為卷帶（TR）剪切帶（CT）Digi-Reel? 得捷定制卷帶；類別為集成電路（IC）的門反相器；產品描述：IC GATE XOR 1CH 2-INP DFN1010-6
功能描述	Low-power 2-input EXCLUSIVE-OR gate
封裝外殼	6-XFDFN
文件大小	274.11 Kbytes
頁面數(shù)量	18 頁
生產廠商	Nexperia B.V. All rights reserved
企業(yè)簡稱	NEXPERIA【安世】
中文名稱	安世半導體(中國)有限公司官網
原廠標識
數(shù)據(jù)手冊	下載地址一下載地址二到原廠下載
更新時間	2025-1-15 12:14:00

1. General description

The 74AUP1G86 is a single 2-input EXCLUSIVE-OR gate. Schmitt-trigger action at all inputs

makes the circuit tolerant of slower input rise and fall times. This device ensures very low static

and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is

fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output,

preventing the potentially damaging backflow current through the device when it is powered down.

2. Features and benefits

? Wide supply voltage range from 0.8 V to 3.6 V

? CMOS low power dissipation

? High noise immunity

? Low static power consumption; ICC = 0.9 μA (maximum)

? Overvoltage tolerant inputs to 3.6 V

? Low noise overshoot and undershoot < 10 of VCC

? IOFF circuitry provides partial power-down mode operation

? Latch-up performance exceeds 100 mA per JESD 78 Class II Level B

? Complies with JEDEC standards:

? JESD8-12 (0.8 V to 1.3 V)

? JESD8-11 (0.9 V to 1.65 V)

? JESD8-7 (1.2 V to 1.95 V)

? JESD8-5 (1.8 V to 2.7 V)

? JESD8-B (2.7 V to 3.6 V)

? ESD protection:

? HBM JESD22-A114F Class 3A exceeds 5000 V

? MM JESD22-A115-A exceeds 200 V

? CDM JESD22-C101E exceeds 1000 V

? Multiple package options

? Specified from -40 °C to +85 °C and -40 °C to +125 °C