74AUP1Z125GW集成電路（IC）的專用邏輯器件規(guī)格書PDF中文資料

1. General description

The 74AUP1Z125 is a crystal driver with enable, internal resistor and 3-state output. When not

in use the EN input can be driven HIGH, putting the device in a low power disable mode with X1

pulled HIGH via RPU, X2 set LOW and Y in the high impedance OFF-state. In disable mode the

output Y assumes the high impedance OFF-state. Schmitt trigger action on the EN input makes the

circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

2. Features and benefits

? Wide supply voltage range from 0.8 V to 3.6 V

? CMOS low power dissipation

? High noise immunity

? Complies with JEDEC standards:

? JESD8-12 (0.8 V to 1.3 V)

? JESD8-11 (0.9 V to 1.65 V)

? JESD8-7 (1.65 V to 1.95 V)

? JESD8-5 (2.3 V to 2.7 V)

? JESD8C (2.7 V to 3.6 V)

? ESD protection:

? HBM JESD22-A114F Class 3A exceeds 5000 V

? MM JESD22-A115-A exceeds 200 V

? CDM JESD22-C101E exceeds 1000 V

? Latch-up performance exceeds 100 mA per JESD78B Class II Level B

? Overvoltage tolerant inputs to 3.6 V

? Low noise overshoot and undershoot < 10 of VCC

? IOFF circuitry provides partial Power-down mode operation at output Y

? Multiple package options

? Specified from -40 °C to +85 °C and -40 °C to +125 °C