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74F113SJ

Dual JK Negative Edge-Triggered Flip-Flop

GeneralDescription The74F113offersindividualJ,K,SetandClockinputs.WhentheclockgoesHIGHtheinputsareenabledanddatamaybeentered. ThelogicleveloftheJandKinputsmaybechangedwhentheclockpulseisHIGHandtheflipflopwillperformaccordingtotheTruthTableaslo

FairchildFairchild Semiconductor

仙童半導體飛兆/仙童半導體公司

74F113

DualJKNegativeEdge-TriggeredFlip-Flop

GeneralDescription The74F113offersindividualJ,K,SetandClockinputs.WhentheclockgoesHIGHtheinputsareenabledanddatamaybeentered. ThelogicleveloftheJandKinputsmaybechangedwhentheclockpulseisHIGHandtheflipflopwillperformaccordingtotheTruthTableaslo

FairchildFairchild Semiconductor

仙童半導體飛兆/仙童半導體公司

74F113

DualJ-Knegativeedge-triggeredflip-flopswithoutreset

DESCRIPTION The74F113,dualnegativeedge-triggeredJK-typeflip-flop,featuresindividualJ,K,clock(CP),set(SD)inputs,trueandcomplementaryoutputs.TheasynchronousSDinput,whenlow,forcestheoutputstothesteadystatelevelsasshowninthefunctiontableregardlessofthelevel

PhilipsNXP Semiconductors

飛利浦荷蘭皇家飛利浦

74F113PC

DualJKNegativeEdge-TriggeredFlip-Flop

GeneralDescription The74F113offersindividualJ,K,SetandClockinputs.WhentheclockgoesHIGHtheinputsareenabledanddatamaybeentered. ThelogicleveloftheJandKinputsmaybechangedwhentheclockpulseisHIGHandtheflipflopwillperformaccordingtotheTruthTableaslo

FairchildFairchild Semiconductor

仙童半導體飛兆/仙童半導體公司

74F113SC

DualJKNegativeEdge-TriggeredFlip-Flop

GeneralDescription The74F113offersindividualJ,K,SetandClockinputs.WhentheclockgoesHIGHtheinputsareenabledanddatamaybeentered. ThelogicleveloftheJandKinputsmaybechangedwhentheclockpulseisHIGHandtheflipflopwillperformaccordingtotheTruthTableaslo

FairchildFairchild Semiconductor

仙童半導體飛兆/仙童半導體公司

I74F113D

DualJ-Knegativeedge-triggeredflip-flopswithoutreset

DESCRIPTION The74F113,dualnegativeedge-triggeredJK-typeflip-flop,featuresindividualJ,K,clock(CP),set(SD)inputs,trueandcomplementaryoutputs.TheasynchronousSDinput,whenlow,forcestheoutputstothesteadystatelevelsasshowninthefunctiontableregardlessofthelevel

PhilipsNXP Semiconductors

飛利浦荷蘭皇家飛利浦

I74F113N

DualJ-Knegativeedge-triggeredflip-flopswithoutreset

DESCRIPTION The74F113,dualnegativeedge-triggeredJK-typeflip-flop,featuresindividualJ,K,clock(CP),set(SD)inputs,trueandcomplementaryoutputs.TheasynchronousSDinput,whenlow,forcestheoutputstothesteadystatelevelsasshowninthefunctiontableregardlessofthelevel

PhilipsNXP Semiconductors

飛利浦荷蘭皇家飛利浦

N74F113D

DualJ-Knegativeedge-triggeredflip-flopswithoutreset

DESCRIPTION The74F113,dualnegativeedge-triggeredJK-typeflip-flop,featuresindividualJ,K,clock(CP),set(SD)inputs,trueandcomplementaryoutputs.TheasynchronousSDinput,whenlow,forcestheoutputstothesteadystatelevelsasshowninthefunctiontableregardlessofthelevel

PhilipsNXP Semiconductors

飛利浦荷蘭皇家飛利浦

N74F113N

DualJ-Knegativeedge-triggeredflip-flopswithoutreset

DESCRIPTION The74F113,dualnegativeedge-triggeredJK-typeflip-flop,featuresindividualJ,K,clock(CP),set(SD)inputs,trueandcomplementaryoutputs.TheasynchronousSDinput,whenlow,forcestheoutputstothesteadystatelevelsasshowninthefunctiontableregardlessofthelevel

PhilipsNXP Semiconductors

飛利浦荷蘭皇家飛利浦

詳細參數(shù)

  • 型號:

    74F113SJ

  • 功能描述:

    觸發(fā)器 Dual J-K Flip-Flop

  • RoHS:

  • 制造商:

    Texas Instruments

  • 電路數(shù)量:

    2

  • 邏輯系列:

    SN74

  • 邏輯類型:

    D-Type Flip-Flop

  • 極性:

    Inverting, Non-Inverting

  • 輸入類型:

    CMOS

  • 傳播延遲時間:

    4.4 ns

  • 高電平輸出電流:

    - 16 mA

  • 低電平輸出電流:

    16 mA

  • 電源電壓-最大:

    5.5 V

  • 最大工作溫度:

    + 85 C

  • 安裝風格:

    SMD/SMT

  • 封裝/箱體:

    X2SON-8

  • 封裝:

    Reel

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onsemi(安森美)
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1612
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3000
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FAIRCHILD
23+
NA
19960
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原廠
2020+
3178
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onsemi(安森美)
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SO14P
2181
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onsemi(安森美)
23+
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更多74F113SJ供應商 更新時間2024-11-20 15:16:00