首頁>74HC237>規(guī)格書詳情

74HC237集成電路（IC）的信號開關多路復用器解碼器規(guī)格書PDF中文資料

廠商型號	74HC237
參數(shù)屬性	74HC237 封裝/外殼為16-SOIC（0.154"，3.90mm 寬）；包裝為卷帶（TR）剪切帶（CT）Digi-Reel? 得捷定制卷帶；類別為集成電路（IC）的信號開關多路復用器解碼器；產品描述：IC DECODER/DEMUX 1 X 3:8 16SO
功能描述	3-to-8 line decoder, demultiplexer with address latches
封裝外殼	16-SOIC（0.154"，3.90mm 寬）
文件大小	276.25 Kbytes
頁面數(shù)量	16 頁
生產廠商	Nexperia B.V. All rights reserved
企業(yè)簡稱	NEXPERIA【安世】
中文名稱	安世半導體(中國)有限公司官網(wǎng)
原廠標識
數(shù)據(jù)手冊	下載地址一下載地址二到原廠下載
更新時間	2025-3-6 22:50:00
人工找貨	74HC237價格和庫存，歡迎聯(lián)系客服免費人工找貨

1. General description

The 74HC237 is a 3-to-8 line decoder, demultiplexer with latches at the three address inputs (An).

The 74HC237 essentially combines the 3-to-8 decoder function with a 3-bit storage latch. When

the latch is enabled (LE = LOW), the 74HC237 acts as a 3-to-8 active LOW decoder. When the

latch enable (LE) goes from LOW-to-HIGH, the last data present at the inputs before this transition,

is stored in the latches. Further address changes are ignored as long as LE remains HIGH. The

output enable input (E1 and E2) controls the state of the outputs independent of the address inputs

or latch operation. All outputs are HIGH unless E1 is LOW and E2 is HIGH. The 74HC237 is ideally

suited for implementing non-overlapping decoders in 3-state systems and strobes (stored address)

applications in bus-oriented systems.

2. Features and benefits

? Combines 3-to-8 decoder with 3-bit latch

? Multiple input enable for easy expansion or independent controls

? Active HIGH mutually exclusive outputs

? Wide supply voltage range from 2.0 V to 6.0 V

? CMOS low power dissipation

? High noise immunity

? Latch-up performance exceeds 100 mA per JESD 78 Class II Level B

? Complies with JEDEC standards:

? JESD8C (2.7 V to 3.6 V)

? JESD7A (2.0 V to 6.0 V)

? ESD protection:

? ? HBM JESD22-A114F exceeds 2000 V

? MM JESD22-A115-A exceeds 200 V

? Multiple package options

? Specified from -40 °C to +85 °C and from -40 °C to +125 °C