1. General description

The 74HC259; 74HCT259 is an 8-bit addressable latch. The device features four modes of

operation. In the addressable latch mode, data on the D input is written into the latch addressed

by the inputs A0 to A3. The addressed latch will follow the data input, non-addressed latches

will retain their previous states. In memory mode, all latches retain their previous states and are

unaffected by the data or address inputs. In the 3-to-8 decoding or demultiplexing mode, the

addressed output follows the D input and all other outputs are LOW. In the reset mode, all outputs

are forced LOW and unaffected by the data or address inputs. Inputs include clamp diodes. This

enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

2. Features and benefits

? Wide supply voltage range from 2.0 V to 6.0 V

? Latch-up performance exceeds 100 mA per JESD 78 Class II Level B

? Complies with JEDEC standards:

? JESD8C (2.7 V to 3.6 V)

? JESD7A (2.0 V to 6.0 V)

? Combined demultiplexer and 8-bit latch

? Serial-to-parallel capability

? Output from each storage bit available

? Random (addressable) data entry

? Easily expandable

? Common reset input

? Useful as a 3-to-8 active HIGH decoder

? Input levels:

? For 74HC259: CMOS level

? For 74HCT259: TTL level

? ESD protection:

? HBM: ANSI/ESDA/Jedec JS-001 Class 2 exceeds 2000 V

? CDM: ANSI/ESDA/Jedec JS-002 Class C3 exceeds 1000 V

? Multiple package options

? Specified from -40 °C to +85 °C and from -40 °C to +125 °C

74HC259PW屬于集成電路（IC） > 鎖存器。安世半導(dǎo)體(中國(guó))有限公司制造生產(chǎn)的74HC259PW鎖存器鎖存器是類似于觸發(fā)器的基本數(shù)字存儲(chǔ)設(shè)備，但是不同之處在于，在鎖存使能（或類似命名）信號(hào)處于有效邏輯狀態(tài)的任何時(shí)間，保持的邏輯狀態(tài)都可以改變。“透明”鎖存器還允許設(shè)備輸出在鎖存使能信號(hào)有效時(shí)反映輸入的當(dāng)前狀態(tài)，而相反的是，狀態(tài)僅在保持狀態(tài)已固定時(shí)改變。