1. General description

The 74HC390; 74HCT390 is a dual 4-bit decade ripple counter divided into four separately clocked

sections. The counters have two divide-by-2 sections and two divide-by-5 sections. These sections

share an asynchronous master reset input (nMR) and can be used in a BCD decade or bi-quinary

configuration. If master reset inputs (1MR and 2MR) are used to simultaneously clear all 8 bits of

the counter, a number of counting configurations are possible within one package. The separate

clocks (nCP0 and nCP1) of each section allow ripple counter or frequency division applications of

divide-by-2, 4, 5, 10, 20, 25, 50 or 100. Each section is triggered by the HIGH-to-LOW transition

of the clock inputs (nCP0 and nCP1). For BCD decade operation, the nQ0 output is connected

to the nCP1 input of the divide-by-5 section. For bi-quinary decade operation, the nQ3 output is

connected to the nCP0 input and nQ0 becomes the decade output. A HIGH on the nMR input

overrides the clocks and sets the four outputs LOW. This device features reduced input threshold

levels to allow interfacing to TTL logic levels. Inputs also include clamp diodes, this enables the use

of current limiting resistors to interface inputs to voltages in excess of VCC.

2. Features and benefits

? Input levels:

? For 74HC390: CMOS level

? For 74HCT390: TTL level

? Two BCD decade or bi-quinary counters

? One device can be configured to divide-by-2, 4, 5, 10, 20, 25, 50 or 100

? Two master reset inputs to clear each decade counter individually

? Supply voltage range from 4.5 V to 5.5 V

? High noise immunity

? Latch-up performance exceeds 100 mA per JESD 78 Class II Level B

? Complies with JEDEC standard JESD7A (4.5 V to 5.5 V)

? ESD protection:

? HBM JESD22-A114F exceeds 2000 V

? MM JESD22-A115-A exceeds 200 V

? Specified from -40 °C to +85 °C and from -40 °C to +125 °C

74HC390屬于集成電路（IC） > 計(jì)數(shù)器，除法器。安世半導(dǎo)體(中國)有限公司制造生產(chǎn)的74HC390計(jì)數(shù)器，除法器計(jì)數(shù)器和除法器 IC 是數(shù)字邏輯器件，可對輸入發(fā)生的邏輯轉(zhuǎn)換進(jìn)行計(jì)數(shù)，然后使用多個(gè)并行輸出重新發(fā)送累加的計(jì)數(shù)，和/或生成單個(gè)輸出信號轉(zhuǎn)換，從而對應(yīng)用某些整數(shù)數(shù)量輸入信號轉(zhuǎn)換進(jìn)行響應(yīng)。除了簡單的事件計(jì)數(shù)，它們還可用于各種頻率合成應(yīng)用。