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74HC73

Dual JK flip-flop with reset; negative-edge trigger

Generaldescription The74HC73isahigh-speedSi-gateCMOSdeviceandispincompatiblewithlow-powerSchottkyTTL(LSTTL).The74HC73isspecifiedincompliancewithJEDECstandardno.7A. Features Low-powerdissipation ComplieswithJEDECstandardno.7A ESDprotection:

PhilipsNXP Semiconductors

飛利浦荷蘭皇家飛利浦

74HC73

Dual JK flip-flop with reset; negative-edge trigger

Generaldescription The74HC73isahigh-speedSi-gateCMOSdevicethatcomplieswithJEDECstandardno.7A.ItispincompatiblewithLow-powerSchottkyTTL(LSTTL).

nxpNXP Semiconductors

恩智浦恩智浦半導(dǎo)體公司

74HC73

Dual JK flip-flop with reset; negative-edge trigger

1.Generaldescription The74HC73isadualnegativeedgetriggeredJKflip-flopwithindividualJ,K,clock(nCP)and reset(nR)inputsandcomplementarynQandnQoutputs.TheJandKinputsmustbestable oneset-uptimepriortotheHIGH-to-LOWclocktransitionforpredictableoperation.(n

NEXPERIANexperia B.V. All rights reserved

安世安世半導(dǎo)體(中國)有限公司

74HC73D

Dual JK flip-flop with reset; negative-edge trigger

Generaldescription The74HC73isahigh-speedSi-gateCMOSdeviceandispincompatiblewithlow-powerSchottkyTTL(LSTTL).The74HC73isspecifiedincompliancewithJEDECstandardno.7A. Features Low-powerdissipation ComplieswithJEDECstandardno.7A ESDprotection:

PhilipsNXP Semiconductors

飛利浦荷蘭皇家飛利浦

74HC73D

Dual JK flip-flop with reset; negative-edge trigger

Generaldescription The74HC73isahigh-speedSi-gateCMOSdevicethatcomplieswithJEDECstandardno.7A.ItispincompatiblewithLow-powerSchottkyTTL(LSTTL).

nxpNXP Semiconductors

恩智浦恩智浦半導(dǎo)體公司

74HC73D

Dual JK flip-flop with reset; negative-edge trigger

1.Generaldescription The74HC73isadualnegativeedgetriggeredJKflip-flopwithindividualJ,K,clock(nCP)and reset(nR)inputsandcomplementarynQandnQoutputs.TheJandKinputsmustbestable oneset-uptimepriortotheHIGH-to-LOWclocktransitionforpredictableoperation.(n

NEXPERIANexperia B.V. All rights reserved

安世安世半導(dǎo)體(中國)有限公司

74HC73DB

Dual JK flip-flop with reset; negative-edge trigger

Generaldescription The74HC73isahigh-speedSi-gateCMOSdeviceandispincompatiblewithlow-powerSchottkyTTL(LSTTL).The74HC73isspecifiedincompliancewithJEDECstandardno.7A. Features Low-powerdissipation ComplieswithJEDECstandardno.7A ESDprotection:

PhilipsNXP Semiconductors

飛利浦荷蘭皇家飛利浦

74HC73DB

Dual JK flip-flop with reset; negative-edge trigger

Generaldescription The74HC73isahigh-speedSi-gateCMOSdevicethatcomplieswithJEDECstandardno.7A.ItispincompatiblewithLow-powerSchottkyTTL(LSTTL).

nxpNXP Semiconductors

恩智浦恩智浦半導(dǎo)體公司

74HC73D-Q100

Dual JK flip-flop with reset; negative-edge trigger

1.Generaldescription The74HC73-Q100isadualnegativeedgetriggeredJKflip-flopwithindividualJ,K,clock(nCP) andreset(nR)inputsandcomplementarynQandnQoutputs.TheJandKinputsmustbe stableoneset-uptimepriortotheHIGH-to-LOWclocktransitionforpredictableoperatio

NEXPERIANexperia B.V. All rights reserved

安世安世半導(dǎo)體(中國)有限公司

74HC73N

Dual JK flip-flop with reset; negative-edge trigger

Generaldescription The74HC73isahigh-speedSi-gateCMOSdeviceandispincompatiblewithlow-powerSchottkyTTL(LSTTL).The74HC73isspecifiedincompliancewithJEDECstandardno.7A. Features Low-powerdissipation ComplieswithJEDECstandardno.7A ESDprotection:

PhilipsNXP Semiconductors

飛利浦荷蘭皇家飛利浦

詳細(xì)參數(shù)

  • 型號：

    74HC73

  • 功能描述：

    觸發(fā)器 DUAL JK F/F NEG-EDGE

  • RoHS：

    否

  • 制造商：

    Texas Instruments

  • 電路數(shù)量：

    2

  • 邏輯系列：

    SN74

  • 邏輯類型：

    D-Type Flip-Flop

  • 極性：

    Inverting, Non-Inverting

  • 輸入類型：

    CMOS

  • 傳播延遲時間：

    4.4 ns

  • 高電平輸出電流：

    - 16 mA

  • 低電平輸出電流：

    16 mA

  • 電源電壓-最大：

    5.5 V

  • 最大工作溫度：

    + 85 C

  • 安裝風(fēng)格：

    SMD/SMT

  • 封裝/箱體：

    X2SON-8

  • 封裝：

    Reel

供應(yīng)商型號品牌批號封裝庫存備注價格
24+
1000
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HIT
23+
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9980
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23+
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50000
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ST
23+
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16900
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MOTOROLA
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6500
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22+
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3000
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23+
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4425
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更多74HC73供應(yīng)商 更新時間2025-1-23 16:00:00

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