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74HC75D集成電路（IC）的鎖存器規(guī)格書PDF中文資料

廠商型號	74HC75D
參數(shù)屬性	74HC75D 封裝/外殼為16-SOIC（0.154"，3.90mm 寬）；包裝為管件；類別為集成電路（IC）的鎖存器；產(chǎn)品描述：IC LATCH QUAD BISTABLE 16SOIC
功能描述	Quad bistable transparant latch
封裝外殼	16-SOIC（0.154"，3.90mm 寬）
文件大小	257.81 Kbytes
頁面數(shù)量	16 頁
生產(chǎn)廠商	Nexperia B.V. All rights reserved
企業(yè)簡稱	NEXPERIA【安世】
中文名稱	安世半導體(中國)有限公司官網(wǎng)
原廠標識
數(shù)據(jù)手冊	下載地址一下載地址二到原廠下載
更新時間	2025-1-11 23:00:00

1. General description

The 74HC75 is a quad bistable transparent latch with complementary outputs. Two latches are

simultaneously controlled by one of two active HIGH enable inputs (LE12 and LE34). When LEnn

is HIGH, the data enters the latches and appears at the nQ outputs. The nQ outputs follow the data

inputs (nD) as long as LEnn is HIGH (transparent). The data on the nD inputs one set-up time prior

to the HIGH-to-LOW transition of the LEnn will be stored in the latches. The latched outputs remain

stable as long as the LEnn is LOW. Inputs include clamp diodes. This enables the use of current

limiting resistors to interface inputs to voltages in excess of VCC.

2. Features and benefits

? Wide supply voltage range from 2.0 V to 6.0 V

? CMOS low power dissipation

? High noise immunity

? Latch-up performance exceeds 100 mA per JESD 78 Class II Level B

? Complies with JEDEC standards:

? JESD8C (2.7 V to 3.6 V)

? JESD7A (2.0 V to 6.0 V)

? Complementary Q and Q outputs

? VCC and GND on the center pins

? CMOS input levels

? ESD protection:

? HBM EIA/JESD22-A114F exceeds 2000 V

? MM EIA/JESD22-A115-A exceeds 200 V

? Specified from -40 °C to +80 °C and from -40 °C to +125 °C.