1. General description

The 74HC107; 74HCT107 is a dual negative edge triggered JK flip-flop featuring individual J and

K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an

asynchronous active LOW input and operates independently of the clock input. The J and K inputs

control the state changes of the flip-flops as described in the mode select function table. The J and

K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable

operation. Inputs include clamp diodes that enable the use of current limiting resistors to interface

inputs to voltages in excess of VCC.

2. Features and benefits

? Wide supply voltage range from 2.0 V to 6.0 V

? CMOS low power dissipation

? High noise immunity

? Latch-up performance exceeds 100 mA per JESD 78 Class II Level B

? Complies with JEDEC standards:

? JESD8C (2.7 V to 3.6 V)

? JESD7A (2.0 V to 6.0 V)

? Input levels:

? The 74HC107: CMOS levels

? The 74HCT107: TTL levels

? ESD protection:

? HBM JESD22-A114F exceeds 2000 V

? MM JESD22-A115-A exceeds 200 V

? Specified from -40 °C to +85 °C and from -40 °C to +125 °C

74HCT107D屬于集成電路（IC） > 觸發(fā)器。安世半導體(中國)有限公司制造生產(chǎn)的74HCT107D觸發(fā)器觸發(fā)器是能夠存儲單個邏輯狀態(tài)或信息“位”的基本數(shù)字存儲器件。這些器件至少有兩個輸入；一個或多個用于傳遞要存儲的數(shù)據(jù)，另一個用于指示存儲該數(shù)據(jù)的時間點。不同的觸發(fā)器類型，例如 D（延遲）、SR（置位復位）和 JK，對提供給其輸入的信號有不同的響應，可用于實現(xiàn)不同的邏輯功能。這些器件與鎖存器的不同之處在于它們是邊緣敏感器件，其保持的邏輯狀態(tài)僅在接收到有效時鐘信號時才會改變。