1. General description

The 74HC112; 74HCT112 is a dual negative-edge triggered JK flip-flop. It features individual J and

K inputs, clock (nCP) set (nSD) and reset (nRD) inputs. It also has complementary nQ and nQ

outputs. The set and reset are asynchronous active LOW inputs and operate independently of the

clock input. The J and K inputs control the state changes of the flip-flops as described in the mode

select function table. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW

clock transition for predictable operation. Inputs include clamp diodes that enable the use of current

limiting resistors to interface inputs to voltages in excess of VCC.

Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall

times.

2. Features and benefits

? Input levels:

? For 74HC112: CMOS level

? For 74HCT112: TTL level

? Asynchronous set and reset

? Specified in compliance with JEDEC standard no. 7A

? ESD protection:

? HBM JESD22-A114F exceeds 2000 V

? MM JESD22-A115-A exceeds 200 V

? Specified from -40 °C to +85 °C and from -40 °C to +125 °C

74HCT112D屬于集成電路（IC） > 觸發(fā)器。安世半導(dǎo)體(中國)有限公司制造生產(chǎn)的74HCT112D觸發(fā)器觸發(fā)器是能夠存儲(chǔ)單個(gè)邏輯狀態(tài)或信息“位”的基本數(shù)字存儲(chǔ)器件。這些器件至少有兩個(gè)輸入；一個(gè)或多個(gè)用于傳遞要存儲(chǔ)的數(shù)據(jù)，另一個(gè)用于指示存儲(chǔ)該數(shù)據(jù)的時(shí)間點(diǎn)。不同的觸發(fā)器類型，例如 D（延遲）、SR（置位復(fù)位）和 JK，對(duì)提供給其輸入的信號(hào)有不同的響應(yīng)，可用于實(shí)現(xiàn)不同的邏輯功能。這些器件與鎖存器的不同之處在于它們是邊緣敏感器件，其保持的邏輯狀態(tài)僅在接收到有效時(shí)鐘信號(hào)時(shí)才會(huì)改變。