74HCT166PW中文資料安世數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

1. General description

The 74HC166; 74HCT166 is an 8-bit serial or parallel-in/serial-out shift register. The device

features a serial data input (DS), eight parallel data inputs (D0 to D7) and a serial output (Q7).

When the parallel enable input (PE) is LOW, the data from D0 to D7 is loaded into the shift register

on the next LOW-to-HIGH transition of the clock input (CP). When PE is HIGH, data enters the

register serially at DS with each LOW-to-HIGH transition of CP. When the clock enable input (CE)

is LOW data is shifted on the LOW-to-HIGH transitions of CP. A HIGH on CE disables the CP input.

Inputs include clamp diodes which enable the use of current limiting resistors to interface inputs to

voltages in excess of VCC.

2. Features and benefits

? Wide supply voltage range from 2.0 V to 6.0 V

? CMOS low power dissipation

? High noise immunity

? Latch-up performance exceeds 100 mA per JESD 78 Class II Level B

? Synchronous parallel-to-serial applications

? Synchronous serial input for easy expansion

? Input levels:

? For 74HC166: CMOS level

? For 74HCT166: TTL level

? Complies with JEDEC standards:

? JESD8C (2.7 V to 3.6 V)

? JESD7A (2.0 V to 6.0 V)

? ESD protection:

? HBM JESD22-A114F exceeds 2000 V

? MM JESD22-A115-A exceeds 200 V

? Specified from -40 °C to +85 °C and from -40 °C to +125 °C