74LS245中文資料仙童半導(dǎo)體數(shù)據(jù)手冊PDF規(guī)格書

General Description

These octal bus transceivers are designed for asynchronous two-way communication between data buses. The control function implementation minimizes external timing requirements. The device allows data transmission from the A Bus to the B Bus or from the B Bus to the A Bus depending upon the logic level at the direction control (DIR) input. The enable input (G) can be used to disable the device so that the buses are effectively isolated.

Features

■Bi-Directional bus transceiver in a high-density 20-pin package

■3-STATE outputs drive bus lines directly

■PNP inputs reduce DC loading on bus lines

■Hysteresis at bus inputs improve noise margins

■Typical propagation delay times, port-to-port 8 ns

■Typical enable/disable times 17 ns

■IOL(sink current) 24 mA

■IOH(source current) ?15 mA