74LS73中文資料摩托羅拉數(shù)據(jù)手冊PDF規(guī)格書

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

TheSN54LS/74LS73A offers individual J, K, clear, and clock inputs.These dualflip-flops aredesigned so that when the clock goes HIGH, the inputs are enabledand data will be accepted. The logic level of the J and K inputs may beallowed to change when the clock pulse is HIGH and the bistable will performaccording to the truth table as long as minimum set-up times are observed.Input data is transferred to the outputs on the negative-going edge of the clock pulse.