74LV107N中文資料飛利浦?jǐn)?shù)據(jù)手冊(cè)PDF規(guī)格書(shū)
74LV107N規(guī)格書(shū)詳情
DESCRIPTION
The 74LV107 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT107.
The 74LV107 is a dual negative-edge triggered JK-type flip-flop featuring individual J, K, clock (nCP) and reset (nR) inputs; also complementary Q and Q outputs.
The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation.
The reset (nR) is an asynchronous active LOW input. When LOW, it overrides the clock and data inputs, forcing the Q output LOW and the Q output HIGH.
Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.
FEATURES
? Wide operating: 1.0 to 5.5 V
? Optimized for low voltage applications: 1.0 to 3.6 V
? Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V
? Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V, Tamb = 25°C
? Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V, Tamb = 25°C
? Output capability: standard
? ICC category: flip-flops
產(chǎn)品屬性
- 型號(hào):
74LV107N
- 制造商:
PHILIPS
- 制造商全稱(chēng):
NXP Semiconductors
- 功能描述:
Dual JK flip-flop with reset; negative-edge trigger
供應(yīng)商 | 型號(hào) | 品牌 | 批號(hào) | 封裝 | 庫(kù)存 | 備注 | 價(jià)格 |
---|---|---|---|---|---|---|---|
TI/TEXAS |
23+ |
TSSOP |
8931 |
詢(xún)價(jià) | |||
TI |
24+ |
35200 |
一級(jí)代理/放心采購(gòu) |
詢(xún)價(jià) | |||
FSC |
TSSOP |
1000 |
正品原裝--自家現(xiàn)貨-實(shí)單可談 |
詢(xún)價(jià) | |||
TI |
2018+ |
SOP |
26976 |
代理原裝現(xiàn)貨/特價(jià)熱賣(mài)! |
詢(xún)價(jià) | ||
TI |
1844+ |
TSSOP |
9852 |
只做原裝正品假一賠十為客戶(hù)做到零風(fēng)險(xiǎn)!! |
詢(xún)價(jià) | ||
PHILIPS |
24+ |
TSSOP14 |
2987 |
只售原裝自家現(xiàn)貨!誠(chéng)信經(jīng)營(yíng)!歡迎來(lái)電! |
詢(xún)價(jià) | ||
ph |
24+ |
N/A |
6980 |
原裝現(xiàn)貨,可開(kāi)13%稅票 |
詢(xún)價(jià) | ||
24+ |
5000 |
公司存貨 |
詢(xún)價(jià) | ||||
TI |
2023+ |
TSSOP16 |
50000 |
原裝現(xiàn)貨 |
詢(xún)價(jià) | ||
PHILIPS |
22+ |
TSSOP14 |
307 |
⊙⊙新加坡大量現(xiàn)貨庫(kù)存,深圳常備現(xiàn)貨!歡迎查詢(xún)!⊙ |
詢(xún)價(jià) |