74LV138PW集成電路（IC）的信號開關多路復用器解碼器規(guī)格書PDF中文資料

General description

The 74LV138 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC138 and 74HCT138. The 74LV138 is a 3-to-8 line decoder/demultiplexer. It accepts three binary weighted address inputs (A0, A1 and A2) and, when enabled, provides eight mutually exclusive active LOW outputs (Y0 to Y7).

Features

■ Wide operating voltage: 1.0 V to 5.5 V

■ Optimized for low voltage applications: 1.0 V to 3.6 V

■ Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V

■ Typical output ground bounce < 0.8 V at VCC = 3.3 V and Tamb = 25 °C

■ Typical HIGH-level output voltage (VOH) undershoot: > 2 V at VCC = 3.3 V and Tamb = 25 °C

■ Demultiplexing capability

■ Multiple input enable for easy expansion

■ Ideal for memory chip select decoding

■ Active LOW mutually exclusive outputs

■ ESD protection:

◆ HBM JESD22-A114E exceeds 2000 V

◆ MM JESD22-A115-A exceeds 200 V

■ Multiple package options

■ Specified from ?40 °C to +85 °C and from ?40 °C to +125 °C