74LV165AD集成電路（IC）的移位寄存器規(guī)格書PDF中文資料

1. General description

The 74LV165A is an 8-bit parallel-load or serial-in shift register with complementary serial

outputs (Q7 and Q7) available from the last stage. When the parallel-load input (PL) is

LOW, parallel data from the inputs D0 to D7 are loaded into the register asynchronously.

When input PL is HIGH, data enters the register serially at the input DS. It shifts one place

to the right (Q0?? Q1?? Q2, etc.) with each positive-going clock transition. This feature

allows parallel-to-serial converter expansion by tying the output Q7 to the input DS of the

succeeding stage.

The clock input is a gate-OR structure which allows one input to be used as an active

LOW clock enable input (CE) input. The pin assignment for the inputs CP and CE is

arbitrary and can be reversed for layout convenience. The LOW-to-HIGH transition of the

input CE should only take place while CP HIGH for predictable operation.

Schmitt-trigger action at all inputs, makes the circuit tolerant for slower input rise and fall

times. It is fully specified for partial-power-down applications using IOFF. The IOFF circuitry

disables the output, preventing the damaging current backflow through the device when it

is powered down.

2. Features and benefits

? Wide supply voltage range from 2.0 V to 5.5 V

? Synchronous parallel-to-serial applications

? Synchronous serial input for easy expansion

? Latch-up performance exceeds 250 mA

? CMOS LOW power consumption

? 5.5 V tolerant inputs/outputs

? Direct interface with TTL levels (2.7 V to 3.6 V)

? Power-down mode

? Complies with JEDEC standards:

? JESD8-5 (2.3 V to 2.7 V)

? JESD8B/JESD36 (2.7 V to 3.6 V)

? JESD8-1A (4.5 V to 5.5 V)

? ESD protection:

? HBM JESD22-A114-A exceeds 2000 V

? MM JESD22-A115-A exceeds 200 V

? Specified from ?40 ?C to +85 ?C