74LVC138APW集成電路（IC）的信號開關(guān)多路復(fù)用器解碼器規(guī)格書PDF中文資料

1. General description

The 74LVC138A decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually

exclusive outputs (Y0 to Y7). The 74LVC138A features three enable inputs (E1, E2 and E3). Every

output will be HIGH unless E1 and E2 are LOW and E3 is HIGH. This multiple enable function

allows easy parallel expansion of the 74LVC138A to a 1-of-32 (5 to 32 lines) decoder with just four

74LVC138A ICs and one inverter. The 74LVC138A can be used as an eight output demultiplexer

by using one of the active LOW enable inputs as the data input and the remaining enable inputs as

strobes. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these

devices as translators in mixed 3.3 V and 5 V environments.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

2. Features and benefits

? Overvoltage tolerant inputs to 5.5 V

? Wide supply voltage range from 1.2 V to 3.6 V

? CMOS low power consumption

? Direct interface with TTL levels

? Demultiplexing capability

? Multiple input enable for easy expansion

? Ideal for memory chip select decoding

? Mutually exclusive outputs

? Output drive capability 50 Ω transmission lines at 125 °C

? Complies with JEDEC standard:

? JESD8-7A (1.65 V to 1.95 V)

? JESD8-5A (2.3 V to 2.7 V)

? JESD8-C/JESD36 (2.7 V to 3.6 V)

? ESD protection:

? HBM JESD22-A114F exceeds 2000 V

? MM JESD22-A115-B exceeds 200 V

? CDM JESD22-C101E exceeds 1000 V

? Specified from -40 °C to +85 °C and from -40 °C to +125 °C