74LVC139PW集成電路（IC）的信號(hào)開關(guān)多路復(fù)用器解碼器規(guī)格書PDF中文資料

1. General description

The 74LVC139 decodes two binary weighted address inputs (nA0, nA1) to four mutually exclusive

outputs (nY0 to nY3). Each decoder features an enable input (nE). When nE is HIGH all outputs

are forced HIGH. The enable input can be used as the data input for a 1-to-4 demultiplexer

application. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of

these devices as translators in mixed 3.3 V and 5 V environments.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

2. Features and benefits

? Wide supply voltage range from 1.2 V to 3.6 V

? Overvoltage tolerant inputs to 5.5 V

? CMOS low power dissipation

? Direct interface with TTL levels

? Demultiplexing capability

? Two independent 2-to-4 decoders

? Multifunction capability

? Mutually exclusive outputs

? Output drive capability 50 Ω transmission lines at 125 °C

? Complies with JEDEC standard:

? ? JESD8-7A (1.65 V to 1.95 V)

? JESD8-5A (2.3 V to 2.7 V)

? JESD8-C/JESD36 (2.7 V to 3.6 V)

? ESD protection:

? HBM JESD22-A114F exceeds 2000 V

? MM JESD22-A115-B exceeds 200 V

? CDM JESD22-C101E exceeds 1000 V

? Multiple package options

? Specified from -40 °C to +85 °C and from -40 °C to +125 °C