74LVC163集成電路（IC）的鎖存器規(guī)格書(shū)PDF中文資料

1. General description

The 74LVC163 is a synchronous presettable binary counter which features an internal look-ahead

carry and can be used for high-speed counting. Synchronous operation is provided by having all

flip-flops clocked simultaneously on the positive-going edge of the clock (pin CP). The outputs (pins

Q0 to Q3) of the counters may be preset to a HIGH-level or LOW-level. A LOW-level at the parallel

enable input (pin PE) disables the counting action and causes the data at the data inputs (pins

D0 to D3) to be loaded into the counter on the positive-going edge of the clock (provided that the

set-up and hold time requirements for PE are met). Preset takes place regardless of the levels at

count enable inputs (pin CEP and CET). A LOW-level at the master reset input (pin MR) sets all

four outputs of the flip-flops (pins Q0 to Q3) to LOW-level after the next positive-going transition

on the clock input (pin CP) (provided that the set-up and hold time requirements for PE are met).

This action occurs regardless of the levels at input pins PE, CET and CEP. This synchronous reset

feature enables the designer to modify the maximum count with only one external NAND gate.

The look-ahead carry simplifies serial cascading of the counters. Both count enable inputs (pin

CEP and CET) must be HIGH in count. The CET input is fed forward to enable the terminal count

output (pin TC). The TC output thus enabled will produce a HIGH output pulse of a duration

approximately equal to a HIGH-level output of Q0. This pulse can be used to enable the next

cascaded stage.

The maximum clock frequency for the cascaded counters is determined by tPHL (propagation delay

CP to TC) and tsu (set-up time CEP to CP) according to the formula: .

2. Features and benefits

? Wide supply voltage range from 1.2 V to 3.6 V

? Inputs accept voltages up to 5.5 V

? CMOS low power consumption

? Direct interface with TTL levels

? Synchronous reset

? Synchronous counting and loading

? Two count enable inputs for n-bit cascading

? Positive edge-triggered clock

? Complies with JEDEC standard:

? JESD8-7A (1.65 V to 1.95 V)

? JESD8-5A (2.3 V to 2.7 V)

? JESD8-C/JESD36 (2.7 V to 3.6 V)

? ESD protection:

? HBM JESD22-A114F exceeds 2000 V

? MM JESD22-A115-B exceeds 200 V

? CDM JESD22-C101E exceeds 1000 V

? Specified from -40 °C to +85 °C and -40 °C to 125 °C