74LVC1G07-Q100中文資料恩智浦數(shù)據(jù)手冊PDF規(guī)格書

General description

The 74LVC1G07-Q100 provides the non-inverting buffer.

The output of this device is an open drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment.

Schmitt-trigger action at all inputs makes the circuit tolerant for slower input rise and fall time.

This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

Features and benefits

■ Automotive product qualification in accordance with AEC-Q100 (Grade 1)

◆ Specified from ?40 °C to +85 °C and from ?40 °C to +125 °C

■ Wide supply voltage range from 1.65 V to 5.5 V

■ 5 V tolerant input/output for interfacing with 5 V logic

■ High noise immunity

■ Complies with JEDEC standard:

◆ JESD8-7 (1.65 V to 1.95 V)

◆ JESD8-5 (2.3 V to 2.7 V)

◆ JESD8-B/JESD36 (2.7 V to 3.6 V)

■ ESD protection:

◆ MIL-STD-883, method 3015 exceeds 2000 V

◆ HBM JESD22-A114F exceeds 2000 V

◆ MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)

■ ?24 mA output drive (VCC = 3.0 V)

■ CMOS low power consumption

■ Latch-up performance exceeds 250 mA

■ Direct interface with TTL levels

■ Inputs accept voltages up to 5 V

■ Multiple package options