74LVC1G79GN集成電路（IC）的觸發(fā)器規(guī)格書PDF中文資料

廠商型號	74LVC1G79GN
參數(shù)屬性	74LVC1G79GN 封裝/外殼為6-XFDFN；包裝為管件；類別為集成電路（IC）的觸發(fā)器；產(chǎn)品描述：IC FF D-TYPE SNGL 1BIT 6XSON
功能描述	Single D-type flip-flop; positive-edge trigger
文件大小	275.95 Kbytes
頁面數(shù)量	19 頁
生產(chǎn)廠商	Nexperia B.V. All rights reserved
企業(yè)簡稱	NEXPERIA【安世】
中文名稱	安世半導體(中國)有限公司官網(wǎng)
原廠標識
數(shù)據(jù)手冊	下載地址一下載地址二到原廠下載
更新時間	2025-1-1 17:02:00

1. General description

The 74LVC1G79 is a single positive-edge triggered D-type flip-flop. Data at the D-input that meets

the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the

flip-flop and appear at the Q output. Inputs can be driven from either 3.3 V or 5 V devices. This

feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device is fully specified for partial power down applications using IOFF. The IOFF circuitry

disables the output, preventing the potentially damaging backflow current through the device when

it is powered down.

2. Features and benefits

? Wide supply voltage range from 1.65 V to 5.5 V

? Overvoltage tolerant inputs to 5.5 V

? High noise immunity

? CMOS low power dissipation

? ±24 mA output drive (VCC = 3.0 V)

? Direct interface with TTL levels

? Latch-up performance exceeds 250 mA

? IOFF circuitry provides partial Power-down mode operation

? Complies with JEDEC standard:

? JESD8-7 (1.65 V to 1.95 V)

? JESD8-5 (2.3 V to 2.7 V)

? JESD8C (2.7 V to 3.6 V)

? JESD36 (4.5 V to 5.5 V)

? ESD protection:

? HBM JESD22-A114F exceeds 2000 V

? MM JESD22-A115-A exceeds 200 V

? Multiple package options

? Specified from -40 °C to +85 °C and -40 °C to +125 °C.