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74LVC2G74集成電路（IC）的觸發(fā)器規(guī)格書PDF中文資料

廠商型號	74LVC2G74
參數(shù)屬性	74LVC2G74 封裝/外殼為8-VFSOP（0.091"，2.30mm 寬）；包裝為卷帶（TR）剪切帶（CT）Digi-Reel? 得捷定制卷帶；類別為集成電路（IC）的觸發(fā)器；產品描述：IC FF D-TYPE SNGL 1BIT 8VSSOP
功能描述	Single D-type flip-flop with set and reset; positive edge trigger
封裝外殼	8-VFSOP（0.091"，2.30mm 寬）
文件大小	278.15 Kbytes
頁面數(shù)量	18 頁
生產廠商	Nexperia B.V. All rights reserved
企業(yè)簡稱	NEXPERIA【安世】
中文名稱	安世半導體(中國)有限公司官網
原廠標識
數(shù)據手冊	下載地址一下載地址二到原廠下載
更新時間	2025-3-9 22:58:00
人工找貨	74LVC2G74價格和庫存，歡迎聯(lián)系客服免費人工找貨

1. General description

The 74LVC2G74 is a single positive edge triggered D-type flip-flop with individual data (D), clock

(CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D-input that

meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in

the flip-flop and appear at the Q output. Inputs can be driven from either 3.3 V or 5 V devices. This

feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device is fully specified for partial power down applications using IOFF. The IOFF circuitry

disables the output, preventing the potentially damaging backflow current through the device when

it is powered down.

2. Features and benefits

? Wide supply voltage range from 1.65 V to 5.5 V

? Overvoltage tolerant inputs to 5.5 V

? High noise immunity

? Complies with JEDEC standard:

? JESD8-7 (1.65 V to 1.95 V)

? JESD8-5 (2.3 V to 2.7 V)

? JESD8-B/JESD36 (2.7 V to 3.6 V)

? ±24 mA output drive (VCC = 3.0 V)

? ESD protection:

? HBM JESD22-A114F exceeds 2000 V

? MM JESD22-A115-A exceeds 200 V

? CMOS low power consumption

? Latch-up performance exceeds 250 mA

? Direct interface with TTL levels

? IOFF circuitry provides partial Power-down mode operation

? Multiple package options

? Specified from -40 °C to +85 °C and -40 °C to +125 °C