74LVC3G17DC集成電路（IC）的緩沖器驅(qū)動器接收器收發(fā)器規(guī)格書PDF中文資料

General description

The 74LVC3G17 provides three non-inverting buffers with Schmitt trigger action. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of the 74LVC3G17 as a translator in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device

when it is powered down.

Features

■ Wide supply voltage range from 1.65 V to 5.5 V

■ 5 V tolerant input/output for interfacing with 5 V logic

■ High noise immunity

■ ESD protection:

◆ HBM JESD22-A114E exceeds 2000 V

◆ MM JESD22-A115-A exceeds 200 V

■ ±24 mA output drive (VCC = 3.0 V)

■ CMOS low-power consumption

■ Latch-up performance exceeds 250 mA

■ Direct interface with TTL levels

■ Multiple package options

■ Specified from ?40 °C to +85 °C and ?40 °C to +125 °C

Applications

■ Wave and pulse shapers for highly noisy environments