74LVC541APW集成電路（IC）的緩沖器驅動器接收器收發(fā)器規(guī)格書PDF中文資料

1. General description

The 74LVC541A is an 8-bit buffer/line driver with 3-state outputs. The device features two

output enables (OE1 and OE2). A HIGH on OEn causes the associated outputs to assume a

high-impedance OFF-state . Inputs can be driven from either 3.3 V or 5 V devices. This feature

allows the use of these devices as translators in mixed 3.3 V and 5 V environments.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device is fully specified for partial power down applications using IOFF. The IOFF circuitry

disables the output, preventing the potentially damaging backflow current through the device when

it is powered down.

2. Features and benefits

? Overvoltage tolerant inputs to 5.5 V

? Wide supply voltage range from 1.2 V to 3.6 V

? CMOS low power consumption

? Direct interface with TTL levels

? IOFF circuitry provides partial Power-down mode operation

? Complies with JEDEC standard:

? JESD8-7A (1.65 V to 1.95 V)

? JESD8-5A (2.3 V to 2.7 V)

? JESD8-C/JESD36 (2.7 V to 3.6 V)

? ESD protection:

? HBM JESD22-A114F exceeds 2000 V

? MM JESD22-A115B exceeds 200 V

? CDM JESD22-C101E exceeds 1000 V

? Specified from -40 °C to +85 °C and -40 °C to +125 °C