74LVC574APW集成電路（IC）的觸發(fā)器規(guī)格書PDF中文資料

1. General description

The 74LVC574A is an 8-bit positive-edge triggered D-type flip-flop with 3-state outputs. The

device features a clock (CP) and output enable (OE) inputs. The flip-flops will store the state of

their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH

clock (CP) transition. A HIGH on OE causes the outputs to assume a high-impedance OFF-state.

Operation of the OE input does not affect the state of the flip-flops. Inputs can be driven from either

3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and

5 V environments.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device is fully specified for partial power down applications using IOFF. The IOFF circuitry

disables the output, preventing the potentially damaging backflow current through the device when

it is powered down.

2. Features and benefits

? Wide supply voltage range from 1.2 to 3.6 V

? CMOS low power consumption

? Direct interface with TTL levels

? Overvoltage tolerant inputs to 5.5 V

? High-impedance when VCC = 0 V

? 8-bit positive edge-triggered register

? Independent register and 3-state buffer operation

? Flow-through pin-out architecture

? IOFF circuitry provides partial Power-down mode operation

? Complies with JEDEC standard:

? JESD8-7A (1.65 V to 1.95 V)

? JESD8-5A (2.3 V to 2.7 V)

? JESD8-C/JESD36 (2.7 V to 3.6 V)

? ESD protection:

? HBM JESD22-A114F exceeds 2000 V

? MM JESD22-A115-B exceeds 200 V

? CDM JESD22-C101E exceeds 1000 V

? Specified from -40 °C to +85 °C and -40 °C to +125 °C