74LVC821A_2中文資料etc未分類制造商數(shù)據(jù)手冊PDF規(guī)格書

General description

The 74LVC821A is a high performance, low power, low voltage Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 V or 5 V devices. In 3-state operation, outputs can handle 5 V. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment.

Features

■ 5 V tolerant inputs and outputs; for interfacing with 5 V logic

■ Wide supply voltage range from 1.2 V to 3.6 V

■ Inputs accept voltages up to 5.5 V

■ CMOS low power consumption

■ Direct interface with TTL levels

■ Flow-through pin-out architecture

■ 10-bit positive edge-triggered register

■ Independent register and 3-state buffer operation

■ Complies with JEDEC standard JESD8-B

■ ESD protection:

◆ HBM EIA/JESD22-A114-B exceeds 2000 V

◆ MM EIA/JESD22-A115-A exceeds 200 V.

■ Specified from ?40 °C to +85 °C and ?40 °C to +125 °C.