74LVCH162244ADGG集成電路（IC）的緩沖器驅(qū)動(dòng)器接收器收發(fā)器規(guī)格書PDF中文資料

1. General description

The 74LVC162244A; 74LVCH162244A is a 16-bit buffer/line driver with 30 Ω termination resistors

and 3-state outputs. The device can be used as four 4-bit buffers, two 8-bit buffers or one 16-bit

buffer. The device features four output enables (1OE, 2OE, 3OE and 4OE), each controlling four of

the 3-state outputs. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices

as translators in mixed 3.3 V and 5 V environments.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device is fully specified for partial power down applications using IOFF. The IOFF circuitry

disables the output, preventing the potentially damaging backflow current through the device when

it is powered down.

The 74LVCH162244A bus hold on data inputs eliminates the need for external pull-up resistors to

hold unused inputs.

2. Features and benefits

? Overvoltage tolerant inputs to 5.5 V

? Wide supply voltage range from 1.2 V to 3.6 V

? CMOS low power dissipation

? Multibyte flow-through standard pin-out architecture

? Low inductance multiple power and ground pins for minimum noise and ground bounce

? Direct interface with TTL levels

? IOFF circuitry provides partial Power-down mode operation

? All data inputs have bus hold. (74LVCH162244A only)

? Complies with JEDEC standard:

? JESD8-7A (1.65 V to 1.95 V)

? JESD8-5A (2.3 V to 2.7 V)

? JESD8-C/JESD36 (2.7 V to 3.6 V)

? ESD protection

? HBM JESD22-A114F exceeds 2000 V

? MM JESD22-A115-B exceeds 200 V

? CDM ANSI/ESDA/Jedec JS-002 exceeds 1000 V

? Specified from -40 °C to +85 °C and -40 °C to +125 °C