74LVCH16373ADGG集成電路（IC）的鎖存器規(guī)格書PDF中文資料

1. General description

The 74LVC16373A and 74LVCH16373A are 16-bit D-type transparent latches with 3-state outputs.

The devices can be used as two 8-bit transparent latches or a single 16-bit transparent latch. The

devices feature two latch enables (1LE and 2LE) and two output enables (1OE and 2OE), each

controlling 8-bits. When nLE is HIGH, data at the inputs enter the latches. In this condition the

latches are transparent, a latch output will change each time its corresponding D-input changes.

When nLE is LOW the latches store the information that was present at the inputs a set-up time

preceding the HIGH-to-LOW transition of nLE. A HIGH on nOE causes the outputs to assume a

high-impedance OFF-state. Operation of the nOE input does not affect the state of the latches.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices

as translators in mixed 3.3 V and 5 V environments.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device is fully specified for partial power down applications using IOFF. The IOFF circuitry

disables the output, preventing the potentially damaging backflow current through the device when

it is powered down.

Bus hold on the data inputs eliminates the need for external pull-up resistors to hold unused inputs.

2. Features and benefits

? Overvoltage tolerant inputs to 5.5 V

? Wide supply voltage range from 1.2 V to 3.6 V

? CMOS low power dissipation

? MULTIBYTE flow-through standard pinout architecture

? Multiple low inductance supply pins for minimum noise and ground bounce

? Direct interface with TTL levels

? All data inputs have bus hold (74LVCH16373A only)

? IOFF circuitry provides partial Power-down mode operation

? Complies with JEDEC standards:

? JESD8-7A (1.65 V to 1.95 V)

? JESD8-5A (2.3 V to 2.7 V)

? JESD8-C/JESD36 (2.7 V to 3.6 V)

? ESD protection:

? HBM JESD22-A114F exceeds 2000 V

? MM JESD22-A115-B exceeds 200 V

? CDM ANSI/ESDA/Jedec JS-002 exceeds 1000 V

? Specified from -40 °C to +85 °C and -40 °C to +125 °C