74LVQ373M集成電路（IC）的鎖存器規(guī)格書PDF中文資料

74LVQ373M屬于集成電路（IC）的鎖存器。由意法半導(dǎo)體集團(tuán)制造生產(chǎn)的74LVQ373M鎖存器鎖存器是類似于觸發(fā)器的基本數(shù)字存儲設(shè)備，但是不同之處在于，在鎖存使能（或類似命名）信號處于有效邏輯狀態(tài)的任何時間，保持的邏輯狀態(tài)都可以改變。“透明”鎖存器還允許設(shè)備輸出在鎖存使能信號有效時反映輸入的當(dāng)前狀態(tài)，而相反的是，狀態(tài)僅在保持狀態(tài)已固定時改變。

DESCRIPTION

The 74LVQ373 is a low voltage CMOS OCTAL D-TYPE LATCH with 3 STATE OUTPUT NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and low noise 3.3V applications.

These 8 bit D-Type latch are controlled by a latch enable input (LE) and an output enable input (OE). While the LE inputs is held at a high level, the Q outputs will follow the data input precisely.

When the LE is taken low, the Q outputs will be latched precisely at the logic level of D input data. While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level) and while high level the outputs will be in a high impedance state.

All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

■ HIGH SPEED:

tPD = 5.8 ns (TYP.) at VCC = 3.3 V

■ COMPATIBLE WITH TTL OUTPUTS

■ LOW POWER DISSIPATION:

ICC = 4 μA (MAX.) at TA=25°C

■ LOW NOISE:

VOLP = 0.4V (TYP.) at VCC = 3.3V

■ 75? TRANSMISSION LINE OUTPUT DRIVE CAPABILITY

■ SYMMETRICAL OUTPUT IMPEDANCE:

|IOH| = IOL = 12mA (MIN) at VCC = 3.0 V

■ PCI BUS LEVELS GUARANTEED AT 24 mA

■ BALANCED PROPAGATION DELAYS: tPLH ? tPHL

■ OPERATING VOLTAGE RANGE:

VCC(OPR) = 2V to 3.6V (1.2V Data Retention)

■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 373

■ IMPROVED LATCH-UP IMMUNITY