74LVQ573_04中文資料意法半導(dǎo)體數(shù)據(jù)手冊PDF規(guī)格書

DESCRIPTION

The 74LVQ573 is a low voltage CMOS OCTAL D-TYPE LATCH with 3 STATE OUTPUTS NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and low noise 3.3V applications.

All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

■ HIGH SPEED:

tPD = 5.8 ns (TYP.) at VCC = 3.3 V

■ COMPATIBLE WITH TTL OUTPUTS

■ LOW POWER DISSIPATION:

ICC = 4 μA (MAX.) at TA=25°C

■ LOW NOISE:

VOLP = 0.5V (TYP.) at VCC = 3.3V

■ 75? TRANSMISSION LINE DRIVING CAPABILITY

■ SYMMETRICAL OUTPUT IMPEDANCE:

|IOH| = IOL = 12mA (MIN) at VCC = 3.0 V

■ PCI BUS LEVELS GUARANTEED AT 24 mA

■ BALANCED PROPAGATION DELAYS: tPLH ? tPHL

■ OPERATING VOLTAGE RANGE:

VCC(OPR) = 2V to 3.6V (1.2V Data Retention)

■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 573

■ IMPROVED LATCH-UP IMMUNITY