74LVT126PW集成電路（IC）的緩沖器驅(qū)動器接收器收發(fā)器規(guī)格書PDF中文資料

1. General description

The 74LVT126 is a quad buffer/line driver with 3-state outputs controlled by the output enable

inputs (nOE). A LOW on nOE causes the outputs to assume a high impedance OFF-state. Bus

hold data inputs eliminate the need for external pull-up resistors to define unused inputs. This

device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables

the output, preventing the potentially damaging backflow current through the device when it is

powered down.

2. Features and benefits

? Quad bus interface

? 3-state buffers

? Wide supply voltage range from 2.7 to 3.6 V

? Overvoltage tolerant inputs to 5.5 V

? BiCMOS high speed and output drive

? Output capability: +64 mA and -32 mA

? Direct interface with TTL levels

? Input and output interface capability to systems at 5 V supply

? Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs

? Live insertion and extraction permitted

? No bus current loading when output is tied to 5 V bus

? Power-up 3-state

? IOFF circuitry provides partial Power-down mode operation

? Latch-up performance exceeds 500 mA per JESD 78 Class II Level B

? Complies with JEDEC standard JESD8C (2.7 V to 3.6 V)

? ESD protection:

? MIL STD 883 method 3015: exceeds 2000 V

? MM: exceeds 200 V