General description

The 74LVT273 is a high-performance BiCMOS product designed for VCC operation at 3.3 V.

This device has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously.

The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output.

All outputs will be forced LOW independent of the clock or data inputs by a LOW voltage level on the MR input. The device is useful for applications where only the true output is required and the CP and MR are common elements.

Features

■ Eight edge-triggered D-type flip-flops

■ Buffered common clock and asynchronous master reset

■ Input and output interface capability to systems at 5 V supply

■ TTL input and output switching levels

■ Input and output interface capability to systems at 5 V supply

■ Output capability: +64 mA/?32 mA

■ Latch-up protection

◆ JESD78 Class II exceeds 500 mA

■ ESD protection:

◆ HBM JESD22-A114E exceeds 2000 V

◆ MM JESD22-A115-A exceeds 200 V

■ Bus-hold data inputs eliminate the need for external pull-up resistors for unused inputs

■ Live insertion/extraction permitted

■ Power-up reset

■ No bus current loading when output is tied to 5 V bus

74LVT273DB屬于集成電路（IC） > 觸發(fā)器。恩智浦半導(dǎo)體公司制造生產(chǎn)的74LVT273DB觸發(fā)器觸發(fā)器是能夠存儲單個邏輯狀態(tài)或信息“位”的基本數(shù)字存儲器件。這些器件至少有兩個輸入；一個或多個用于傳遞要存儲的數(shù)據(jù)，另一個用于指示存儲該數(shù)據(jù)的時間點(diǎn)。不同的觸發(fā)器類型，例如 D（延遲）、SR（置位復(fù)位）和 JK，對提供給其輸入的信號有不同的響應(yīng)，可用于實(shí)現(xiàn)不同的邏輯功能。這些器件與鎖存器的不同之處在于它們是邊緣敏感器件，其保持的邏輯狀態(tài)僅在接收到有效時鐘信號時才會改變。