74LVT640PW集成電路（IC）的緩沖器驅(qū)動器接收器收發(fā)器規(guī)格書PDF中文資料

廠商型號	74LVT640PW
參數(shù)屬性	74LVT640PW 封裝/外殼為20-TSSOP（0.173"，4.40mm 寬）；包裝為卷帶（TR）剪切帶（CT）Digi-Reel? 得捷定制卷帶；類別為集成電路（IC）的緩沖器驅(qū)動器接收器收發(fā)器；產(chǎn)品描述：IC TXRX INVERT 3.6V 20TSSOP
功能描述	3.3 V Octal transceiver with direction pin; inverting; 3-state
文件大小	233.5 Kbytes
頁面數(shù)量	12 頁
生產(chǎn)廠商	Nexperia B.V. All rights reserved
企業(yè)簡稱	NEXPERIA【安世】
中文名稱	安世半導體(中國)有限公司官網(wǎng)
原廠標識
數(shù)據(jù)手冊	下載地址一下載地址二到原廠下載
更新時間	2024-12-27 16:20:00

1. General description

The 74LVT640 is an 8-bit inverting transceiver with 3-state outputs. The device features an output

enable (OE) and send/receive (DIR) for direction control. A HIGH on OE causes the outputs to

assume a high-impedance OFF-state. Bus hold data inputs eliminate the need for external pull-up

resistors to define unused inputs

2. Features and benefits

? 3-state buffers

? Wide supply voltage range from 2.7 to 3.6 V

? Overvoltage tolerant inputs to 5.5 V

? BiCMOS high speed and output drive

? Direct interface with TTL levels

? IOFF circuitry provides partial Power-down mode operation

? Octal bidirectional bus interface

? Input and output interface capability to systems at 5 V supply

? Output capability: +64 mA and -32 mA

? Bus-hold data inputs eliminate the need for external pull-up resistors for unused inputs

? Live insertion/extraction permitted

? Power-up 3-state

? No bus current loading when output is tied to 5 V bus

? Latch-up performance exceeds 500 mA per JESD 78 Class II Level B

? Complies with JEDEC standards

? JESD8C (2.7 V to 3.6 V)

? ESD protection:

? MIL STD 883 method 3015: exceeds 2000 V

? MM JESD22-A115-A exceeds 200 V

? Specified from -40 °C to +85 °C