74LVX161284AMTX集成電路（IC）的專用邏輯器件規(guī)格書PDF中文資料

General Description

The LVX161284A contains eight bidirectional data buffers and eleven control/status buffers to implement a full IEEE 1284 compliant interface. The device supports the IEEE 1284 standard, with the exception of output slew rate, and is intended to be used in an Extended Capabilities Port mode (ECP). The pinout allows for easy connection from the Peripheral (A-side) to the Host (cable side).

Outputs on the cable side can be configured to be either open drain or high drive (r 14 mA) and are connected to a separate power supply pin (VCCcable) to allow these outputs to be driven by a higher supply voltage than the A side. The pull-up and pull-down series termination resistance of these outputs on the cable side is optimized to drive an external cable. In addition, all inputs (except HLH) and outputs on the cable side contain internal pull-up resistors connected to the VCCcable supply to provide proper termination and pull-ups for open drain mode.

Outputs on the Peripheral side are standard low-drive CMOS outputs designed to interface with 3V logic. The DIR input controls data flow on the A1–A8/B1–B8 transceiver pins.

Features

■ Supports IEEE 1284 Level 1 and Level 2 signaling

standards for bidirectional parallel communications

between personal computers and printing peripherals

with the exception of output slew rate

■ Translation capability allows outputs on the cable side to

interface with 5V signals

■ All inputs have hysteresis to provide noise margin

■ B and Y output resistance optimized to drive external cable

■ B and Y outputs in high impedance mode during power down

■ Inputs and outputs on cable side have internal pull-up resistors

■ Flow-through pin configuration allows easy interface

between the “Peripheral and Host”

■ Replaces the function of two (2) 74ACT1284 devices