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74V2G132中文資料意法半導(dǎo)體數(shù)據(jù)手冊(cè)PDF規(guī)格書

74V2G132
廠商型號(hào)

74V2G132

功能描述

DUAL 2-INPUT SHMITT TRIGGER NAND GATE

文件大小

204.23 Kbytes

頁面數(shù)量

9

生產(chǎn)廠商 STMicroelectronics
企業(yè)簡(jiǎn)稱

STMICROELECTRONICS意法半導(dǎo)體

中文名稱

意法半導(dǎo)體集團(tuán)官網(wǎng)

原廠標(biāo)識(shí)
數(shù)據(jù)手冊(cè)

下載地址一下載地址二到原廠下載

更新時(shí)間

2025-1-16 20:00:00

74V2G132規(guī)格書詳情

DESCRIPTION

The 74V2G132 is an advanced high-speed CMOS SINGLE 2-INPUT NAND GATE fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS tecnology.

Pin configuration and function are the same as those of the 74V2G00 but the 74V2G132 has hysteresis.

The internal circuit is composed of 3 stages including buffer output, which provide high noise immunity and stable output.

Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V.

■ HIGH SPEED: tPD = 3.0ns (TYP.) at VCC = 5V

■ LOW POWER DISSIPATION: ICC = 1μA(MAX.) at TA=25°C

■ TYPICAL HYSTERESIS:

VH = 800mV at VCC = 4.5V

VH = 500mV at VCC = 3.0V

■ POWER DOWN PROTECTION ON INPUTS AND OUTPUTS

■ SYMMETRICAL OUTPUT IMPEDANCE:

|IOH| = IOL = 8mA (MIN) at VCC = 4.5V

IIOH| = IOL = 4mA (MIN) at VCC = 3.0V

■ BALANCED PROPAGATION DELAYS: tPLH ? tPHL

■ OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 5.5V

■ IMPROVED LATCH-UP IMMUNITY

產(chǎn)品屬性

  • 型號(hào):

    74V2G132

  • 功能描述:

    DUAL 2-INPUT SHMITT TRIGGER NAND GATE

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