首頁>74V2T132>規(guī)格書詳情

74V2T132中文資料意法半導(dǎo)體數(shù)據(jù)手冊PDF規(guī)格書

74V2T132
廠商型號(hào)

74V2T132

功能描述

DUAL 2-INPUT SHMITT TRIGGER NAND GATE

文件大小

130.419 Kbytes

頁面數(shù)量

7

生產(chǎn)廠商 STMicroelectronics
企業(yè)簡稱

STMICROELECTRONICS意法半導(dǎo)體

中文名稱

意法半導(dǎo)體集團(tuán)官網(wǎng)

原廠標(biāo)識(shí)
數(shù)據(jù)手冊

下載地址一下載地址二到原廠下載

更新時(shí)間

2025-2-5 8:30:00

74V2T132規(guī)格書詳情

DESCRIPTION

The 74V2T132 is an advanced high-speed CMOS SINGLE 2-INPUT NAND GATE fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS tecnology.

Pin configuration and function are the same as those of the 74V2T00 but the 74V2T132 has hysteresis.

The internal circuit is composed of 3 stages including buffer output, which provide high noise immunity and stable output.

Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V.

■ HIGH SPEED: tPD = 3.7 ns (TYP.) at VCC = 5V

■ LOW POWER DISSIPATION: ICC = 1 μA (MAX.) at TA=25°C

■ TYPICAL HYSTERESIS : 0.8V at VCC = 4.5V

■ SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8 mA (MIN)

■ BALANCED PROPAGATION DELAYS: tPLH ? tPHL

■ OPERATING VOLTAGE RANGE: VCC(OPR) = 4.5V to 5.5V

■ IMPROVED LATCH-UP IMMUNITY

產(chǎn)品屬性

  • 型號(hào):

    74V2T132

  • 功能描述:

    DUAL 2-INPUT SHMITT TRIGGER NAND GATE

供應(yīng)商 型號(hào) 品牌 批號(hào) 封裝 庫存 備注 價(jià)格
STMicroelectronics
18+
ICINVERTERTRIPLESOT23-8
6580
公司原裝現(xiàn)貨
詢價(jià)
ST
17+
SOT23-8
6200
100%原裝正品現(xiàn)貨
詢價(jià)
ST/意法
23+
NA/
5050
原裝現(xiàn)貨,當(dāng)天可交貨,原型號(hào)開票
詢價(jià)
ST
TO23
608900
原包原標(biāo)簽100%進(jìn)口原裝常備現(xiàn)貨!
詢價(jià)
ST
24+
SOT23-8
1337
詢價(jià)
ST
22+
SOT23-8
37047
原裝正品現(xiàn)貨,可開13個(gè)點(diǎn)稅
詢價(jià)
ST
23+
SOT23-8
16900
正規(guī)渠道,只有原裝!
詢價(jià)
ST
22+
SOT23-8
16900
支持樣品 原裝現(xiàn)貨 提供技術(shù)支持!
詢價(jià)
ST/意法
22+
N
28000
原裝現(xiàn)貨只有原裝.假一罰十
詢價(jià)
ST
23+
SOT23-8
1000
全新原裝正品
詢價(jià)