74VHC9125FT集成電路（IC）的緩沖器驅(qū)動器接收器收發(fā)器規(guī)格書PDF中文資料

Functional Description

? 5-Bit Universal Schmitt Buffer with 3-State Outputs

General

The 74VHC9125FT/74VHC9126FT are an ultra-high-speed 5-bit Schmitt buffer fabricated using silicon-gate

CMOS technology. The 74VHC9125FT/74VHC9126FT combines low power consumption of CMOS with Schottky

TTL speeds.

Y1 to Y4 outputs can be put in the high-impedance state by placing a logic HIGH on the Enable (G) input. The

CONT input determines the logical inversion of data. A logic LOW on the CONT input configures the

74VHC9125FT/74VHC9126FT as an inverter; a logic HIGH on the CONT input configures the

74VHC9125FT/74VHC9126FT as a buffer.

74VHC9125FT Y5 output is an inverting type, and the 74VHC9126FT Y5 output is a non-inverting type.

All the inputs have hysteresis between the positive-going and negative-going thresholds. Thus the

74VHC9125FT/74VHC9126FT are capable of squaring up transitions of slowly changing input signals and

provides an improved noise immunity.

Additionally, all the inputs have a newly developed protection circuit without a diode returned to VCC. This

enables the inputs to be tolerant of up to 5 volts even when power supply is down. The input power-down protection

capability makes the 74VHC9125FT/74VHC9126FT ideal for a wide range of applications, such as interfacing

between different voltages, voltage translation from 5 V to 3 V and battery back-up circuits.

Features

(1) AEC-Q100 (Rev. H) (Note 1)

(2) Wide operating temperature range: Topr = -40 to 125

(3) High speed: tpd = 5.0 ns (typ.) at VCC = 5.0 V

(4) Low supply current: ICC = 2.0 μA (max) (Ta = 25 )

(5) All inputs are provided with power-down protection.

(6) Symmetrical rise and fall delays: tPLH ? tPHL

(7) Wide operating voltage range: VCC(opr) = 2.0 V to 5.5 V