74VHCT138AFT中文資料東芝數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

Functional Description

? 3-to-8 Line Decoder

General

The 74VHCT138AFT is an advanced high speed CMOS 3-to-8 LINE DECODER fabricated with silicon gate

C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while

maintaining the CMOS low power dissipation.

When the device is enabled, 3 Binary Select inputs (A, B and C) determine which one of the outputs (Y0 to Y7)

will go low.

When enable input G1 is held low or either G2A or G2B is held high, decoding function is inhibited and all outputs

go high. G1, G2A, and G2B inputs are provided to ease cascade connection and for use as an address decoder for

memory systems.

The input voltage are compatible with TTL output voltage.

This device may be used as a level converter for interfacing 3.3 V to 5 V system.

Input protection and output circuit ensure that 0 to 5.5 V can be applied to the input and output (Note) pins

without regard to the supply voltage. These structure prevents device destruction due to mismatched supply and

input/output voltages such as battery back up, hot board insertion, etc.

Note: VCC = 0 V

Features

(1) AEC-Q100 (Rev. H) (Note 1)

(2) Wide operating temperature range: Topr = -40 to 125 

(3) High speed: tpd = 7.6 ns (typ.) at VCC = 5.0 V

(4) Low power dissipation: ICC = 4.0 μA (max) at Ta = 25 

(5) Compatible with TTL inputs : VIL = 0.8 V (max)

: VIH = 2.0 V (min)

(6) Power down protection is provided on all inputs and outputs.

(7) Balanced propagation delays: tPLH ≈ tPHL

(8) Pin and function compatible with 74 series(AC/HC/AHC/LV etc.)138 type.