79RC32333中文資料瑞薩數(shù)據(jù)手冊(cè)PDF規(guī)格書

Device Overview

The RC32333 device is a member of the IDT? Interprise? family of

integrated communications processors. This product incorporates a

high-performance, low-cost 32-bit CPU core with functionality common

to a large number of embedded applications. The RC32333 integrates

these functions to enable the use of low-cost PC commodity market

memory and I/O devices, allowing the aggressive price/performance

characteristics of the CPU to be realized quickly into low-cost systems.

The RC32333 device is available with either a 3.3V or 2.5V operating

voltage. Differences between the two versions are noted where applicable.

Features

◆ RC32300 32-bit Microprocessor

– Up to 150 MHz operation

– Enhanced MIPS-II Instruction Set Architecture (ISA)

– Cache prefetch instruction

– Conditional move instruction

– DSP instructions

– Supports big or little endian operation

– MMU with 32 page TLB

– 8KB Instruction Cache, 2-way set associative

– 2KB Data Cache, 2-way set associative

– Cache locking per line

– Programmable on a page basis to implement a write-through

no write allocate, write-through write allocate, or write-back

algorithms for cache management

– Compatible with a wide variety of operating systems

◆ Local Bus Interface

– Up to 75 MHz operation

– 23-bit address bus

– 32-bit data bus

– Direct control of local memory and peripherals

– Programmable system watch-dog timers

– Big or little endian support

◆ Interrupt Controller simplifies exception management

◆ Four general purpose 32-bit timer/counters

◆ Programmable I/O (PIO)

– Input/Output/Interrupt source

– Individually programmable

◆ SDRAM Controller (32-bit memory only)

– 4 banks, non-interleaved

– Up to 512MB total SDRAM memory supported

– Implements full, direct control of discrete, SODIMM, or DIMM

memories

– Supports 16Mb through 512Mb SDRAM device depths

– Automatic refresh generation