79RC32T336150BCGI中文資料瑞薩數(shù)據(jù)手冊PDF規(guī)格書

Device Overview

The RC32336 device is a member of the IDT? Interprise? family of

integrated communications processors. It provides an effective solution

for small office/home office (SOHO) applications including gateways and

both single-band and dual-band wireless access points. Featuring a

MIPS compatible CPU core, the device also includes a memory

controller supporting SDRAM memory, a PCI interface featuring an onchip

arbiter to support up to three external devices, a PCMCIA interface

that supports a single I/O device, and two integrated on-chip 10/100

Ethernet MACs to enable WAN and LAN connectivity.

The key features of the RC32336 enable SOHO applications at

unmatched price/performance points. The MIPS-compatible CPU core

has the required bandwidth to enable a WAP application with the latest

wireless security protocols, WPA and 802.11i, which include the enterprise-

level user authentication schemes 802.1x and Extensible Authentication

Protocol (EAP). The ability to connect and support the bandwidth

requirements of one or two WLAN modules is made possible by the high

bandwidth PCI and PCMCIA interfaces. Also, the device has been architected

to provide high speed LAN to WAN routing bandwidth through the

Ethernet MACs while simultaneously driving data through the other onchip

interfaces.

Features List

RC32300 32-bit CPU core

– 32-bit MIPS instruction set

– Supports big or little endian operation

– MMU

– 16-entry TLB

– Supports variable page sizes and enhanced write algorithm

– Supports variable number of locked entries

– 8KB Instruction Cache

– 2-way set associative

– LRU replacement algorithm

– 4 word line size

– Sub-block ordering

– Word parity

– Per line cache locking

– 2KB Data Cache

– 2-way set associative

– LRU replacement algorithm

– 4 word line size

– Sub-block ordering

– Byte parity

– Per line cache locking

– Can be programmed on a page basis to implement writethrough

no write allocate, write-through write allocate, or

write-back algorithms

– Enhanced EJTAG and JTAG Interfaces

– Compatible with IEEE Std. 1149.1-1990