79RC32T365-150BC中文資料瑞薩數據手冊PDF規(guī)格書

Device Overview

The RC32365 device is a member of the IDT? Interprise? family of

integrated communications processors. This device is designed to

address a range of communications applications that require the efficient

processing of IPSec algorithms. These applications include gateways,

wireless access points, and virtual private network (VPN)

equipment. The key to the RC32365’s efficient processing of IPSec

algorithms is a highly progammable security engine which off-loads the

CPU core of encryption/decryption, hashing, and padding tasks.

Features List

◆ RC32300 32-bit CPU core

– 32-bit MIPS instruction set

– Supports big or little endian operation

– MMU

– 16-entry TLB

– Supports variable page sizes and enhanced write algorithm

– Supports variable number of locked entries

– 8KB Instruction Cache

– 2-way set associative

– LRU replacement algorithm

– 4 word line size

– Sub-block ordering

– Word parity

– Per line cache locking

– 2KB Data Cache