7C1359A-133中文資料賽普拉斯數(shù)據(jù)手冊PDF規(guī)格書

Functional Description

The Cypress Synchronous Burst SRAM family employs high-speed, low power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high valued resistors.

Features

? Fast match times: 3.5, 3.8, 4.0 and 4.5 ns

? Fast clock speed: 166, 150, 133, and 100 MHz

? Fast OE access times: 3.5, 3.8, 4.0 and 5.0 ns

? Pipelined data comparator

? Data input register load control by DEN

? Optimal for depth expansion (one cycle chip deselect to eliminate bus contention)

? 3.3V –5 and +10 core power supply

? 2.5V or 3.3V I/O supply

? 5V tolerant inputs except I/Os

? Clamp diodes to VSS at all inputs and outputs

? Common data inputs and data outputs

? JTAG boundary scan

? Byte Write Enable and Global Write control

? Three chip enables for depth expansion and address pipeline

? Address, data, and control registers

? Internally self-timed Write Cycle

? Burst control pins (interleaved or linear burst sequence)

? Automatic power-down for portable applications

? Low-profile JEDEC standard 100-pin TQFP package