82595TX中文資料英特爾數(shù)據(jù)手冊PDF規(guī)格書

INTRODUCTION

82595TX Overview

The 82595TX is a highly integrated, high performance LAN controller which provides a cost effective LAN solution for ISA compatible Personal Computer (PC) motherboards (both desktop and portable), add-on ISA adapter boards, and PCMCIA cards. The 82595TX integrates all of the major functions of a buffered LAN solution into one chip with the exception of the local buffer memory, which is implemented by adding one DRAM component to the LAN solution. The 82595TX’s new Concurrent Processing feature significantly enhances throughput performance. Both system bus and serial link activities occur concurrently, allowing the 82595TX to maximize network bandwidth by minimizing delays associated with transmit or receiving frames. The 82595TX’s bus interface is a glueless attachment to either an ISA or PCMCIA version 2.0 bus. Its serial interface provides a Twisted Pair Ethernet (TPE) and an Attachment Unit Interface (AUI) connection. By integrating the majority of the LAN solution functions into one cost effective component, production cost saving can be achieved as well as significantly decreasing the design time for a solution. This level of integration also allows an 82595TX solution to be ported between different applications (PC motherboards, adapters, and PCMCIA IO cards), while maintaining a compatible hardware and software base. This results in further savings in both hardware and software development costs for manufacturers expanding into different applications i.e., an ISA adapter vendor producing PCMCIA IO cards, etc.

■ Optimal Integration for Lowest Cost Solution

— Glueless 8-Bit/16-Bit ISA/PCMCIA 2.0 Bus Interface

— Provides Fully 802.3 Compliant AUI and TPE Serial Interface

— Local DRAM Support up to 64 Kbytes

— FLASH/EPROM Boot Support up to 1 Mbyte for Diskless Workstations

— Hardware and Software Portable between Motherboard, Adapter, and PCMCIA LAN Card Solution

■ High Performance Networking Functions

— Concurrent Processing Functionality for Enhanced Performance

— 16-Bit/32-Bit IO Accesses to Local DRAM with Zero Added Wait-States

— Ring Buffer Structure for Continuous Frame Reception and Transmit Chaining

— Automatic Retransmission on Collision

— Automatically Corrects TPE Polarity Switching Problems

■ Low Power CHMOS IV Technology

■ Ease of Use

— Integrated Plug N’ PlayTM Hardware Functionality

— EEPROM Interface to Support Jumperless Designs

— Software Structures Optimized to Reduce Processing Steps

— Automatically Maps into Unused PC IO Locations to Help Eliminate LAN Setup Problems

— All Software Structures Contained in One 16-Byte IO Space

— JTAG Port for Reduced Board Testing Times

— Automatic or Manual Switching between TPE and AUI Ports

■ Power Management

— SL Compatible SMOUT Power Down Input

— Software Power Down Command for Non-SL Systems

■ 144-Lead tQFP Package Provides Smallest Available Form Factor

■ 100 Backwards Hardware/Software Compatible to 82595