8534-01中文資料瑞薩數(shù)據(jù)手冊PDF規(guī)格書

Features

? Twenty-two differential LVPECL outputs

? Selectable differential CLK, nCLK or LVPECL clock inputs

? CLK, nCLK pair can accept the following differential input levels:

LVPECL, LVDS, LVHSTL, HCSL, SSTL

? PCLK, nPCLK supports the following input levels: LVPECL, CML,

SSTL

? Maximum output frequency: 500MHz

? Output skew: 100ps (maximum)

? Translates any single-ended input signal (LVCMOS, LVTTL, GTL)

to LVPECL levels with resistor bias on nCLK input

? Additive phase jitter, RMS): 0.15ps (typical)

? Full 3.3V supply mode

? 0°C to 85°C ambient operating temperature

? Available in lead-free (RoHS 6) package