87016I中文資料瑞薩數(shù)據(jù)手冊PDF規(guī)格書

Features

? Sixteen LVCMOS/LVTTL outputs (4 banks of 4 outputs)

? Selectable differential CLK1/CLK1 or LVCMOS/LVTTL clock input

? CLK1, CLK1 pair can accept the following differential

input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL

? CLK0 supports the following input types: LVCMOS, LVTTL

? Maximum output frequency: 250MHz

? Independent bank control for ÷1 or ÷2 operation

? Independent output bank voltage settings for 3.3V, 2.5V, or 1.8V

operation

? Asynchronous clock enable/disable

? Output skew: 170ps (maximum)

? Bank skew: 50ps (maximum

? Part-to-Part Skew: 800ps (maximum)

? Supply modes:

Core/Output

3.3V/3.3V

3.3V/2.5V

3.3V/1.8V

2.5V/2.5V

2.5V/1.8V

? -40°C to 85°C ambient operating temperature

? Lead-free packaging