874002-02中文資料瑞薩數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

GENERAL DESCRIPTION

The ICS874002-02 is a high performance

Differential-to-LVDS Jitter Attenuator designed for

use in PCI Express? systems. In some PCI

Express? systems, such as those found in desktop

PCs, the PCI Express? clocks are generated from

a low bandwidth, high phase noise PLL frequency synthesizer.

In these systems, a jitter attenuator may be required to

attenuate high frequency random and deterministic jitter

components from the PLL synthesizer and from the system

board. The ICS874002-02 has 2 PLL bandwidth modes: 2.2MHz

and 3MHz. The 2.2MHz mode will provide maximum jitter

attenuation, but with higher PLL tracking skew and spread

spectrum modulation from the motherboard synthesizer may

be attenuated. The 3MHz bandwidth provides the best tracking skew and will pass most spread profiles, but the jitter

attenuation will not be as good as the lower bandwidth modes.

The 874002-02 can be set for differential modes using the

F_SELx pins as shown in Table 3C.

The ICS874002-02 uses IDT’s 3rd Generation FemtoClockTM

PLL technology to achieve the lowest possible phase noise.

The device is packaged in a 20 Lead TSSOP package, making

it ideal for use in space constrained applications such as PCI

Express add-in cards.

FEATURES

? Two differential LVDS output pairs

? One differential clock input

? CLK and nCLK supports the following input types:

LVPECL, LVDS, LVHSTL, SSTL, HCSL

? Output frequency range: 98MHz - 640MHz

? Input frequency range: 98MHz - 128MHz

? VCO range: 490MHz - 640MHz

? Cycle-to-cycle jitter: 50ps (maximum) design target

? 3.3V operating supply

? Two bandwidth modes allow the system designer to make

jitter attenuation/tracking skew design trade-offs

? 0°C to 70°C ambient operating temperature

? Available in lead-free (RoHS 6) package