8761I中文資料瑞薩數(shù)據(jù)手冊(cè)PDF規(guī)格書

Features

? Fully integrated PLL

? Seventeen LVCMOS/LVTTL outputs, 15Ω typical output

impedance

? Selectable crystal oscillator interface or LVCMOS/LVTTL

REF_CLK

? Maximum output frequency: 166.67MHz

? Maximum crystal input frequency: 40MHz

? Maximum REF_CLK input frequency: 83.33MHz

? Individual banks with selectable output dividers for generating

33.333MHz, 66.66MHz, 100MHz and 133.333MHz

simultaneously

? Separate feedback control for generating PCI / PCI-X

frequencies from a 20MHz or 25MHz crystal or 33.333MHz or

66.666MHz reference frequency

? Cycle-to-cycle jitter: 70ps (maximum)

? Period jitter, RMS: 17ps (maximum)

? Output skew: 250ps (maximum)

? Bank skew: 50ps (maximum)

? Static phase offset: 0 ± 150ps (maximum)

? Full 3.3V or 3.3V core, 2.5V multiple output supply modes

? -40°C to 85°C ambient operating temperature

? Available in both standard and lead-free RoHS-compliant

packages