88P8342BHGI集成電路（IC）的專用IC規(guī)格書PDF中文資料

FEATURES

? Functionality

- Low speed to high speed SPI exchange device

- Logical port (LP) mapping (SPI-3 SPI-4) tables per direction

- Per LP configurable memory allocation

- Maskable interrupts for fatal errors

- Fragment and burst length configurable per interface: min 16 bytes,

max 256 bytes

? Standard Interfaces

- Two OIF SPI-3: 8 or 32 bit, 19.44-133 MHz, 256 address range, 64

concurrently active LPs per interface

- One OIF SPI-4 phase 2: 80 - 400 MHz, 256 address range, 128

concurrently active LPs

- SPI-4 FIFO status channel options:

? LVDS full-rate

? LVTTL eighth-rate

- Compatible with Network Processor Streaming Interface (NPSI)

NPE-Framer mode of operation

- SPI-4 ingress LVDS automatic bit alignment and lane de-skew over

the entire frequency range

- SPI-4 egress LVDS programmable lane pre-skew 0.1 to 0.3 cycle

- IEEE 1149.1 JTAG

- Serial or parallel microprocessor interface for control and monitoring

? Full Suite of Performance Monitoring Counters

- Number of packets

- Number of fragments