89H48H12AG2ZCBLGI集成電路（IC）的專用規(guī)格書PDF中文資料

Features

? High Performance Non-Blocking Switch Architecture

– 48-lane 12-port PCIe switch

? Six x8 ports switch ports each of which can bifurcate to two

x4 ports (total of twelve x4 ports)

– Integrated SerDes supports 5.0 GT/s Gen2 and 2.5 GT/s

Gen1 operation

– Delivers up to 48 GBps (384 Gbps) of switching capacity

– Supports 128 Bytes to 2 KB maximum payload size

– Low latency cut-through architecture

– Supports one virtual channel and eight traffic classes

? Standards and Compatibility

– PCI Express Base Specification 2.0 compliant

– Implements the following optional PCI Express features

? Advanced Error Reporting (AER) on all ports

? End-to-End CRC (ECRC)

? Access Control Services (ACS)

? Power Budgeting Enhanced Capability

? Device Serial Number Enhanced Capability

? Sub-System ID and Sub-System Vendor ID Capability

? Internal Error Reporting ECN

? Multicast ECN

? VGA and ISA enable

? L0s and L1 ASPM

? ARI ECN

? Port Configurability

– x4 and x8 ports

? Ability to merge adjacent x4 ports to create a x8 port

– Automatic per port link width negotiation (x8 ? x4 ? x2 ? x1)

– Crosslink support

– Automatic lane reversal

– Autonomous and software managed link width and speed control

– Per lane SerDes configuration